DFFSR
Edge-triggered register bank with configurable reset and set
Description
Connections
Parameters
Modelica Standard Library
The DFFSR component is an edge-triggered digital flip-flop register with configurable reset and set inputs. A positive transition (1-Trns) of the clock causes the input data to be latched and appear at the output.
Truth Table for active-low reset and set
DataIn
Clock
Reset
Set
DataOut
Map
*
U
1
0
2
3
X
6
X or U
4
X or U or 1 or NC
5
X or U or 0 or NC
7
X-Trns
X or U or NC
8
1-Trns
0-Trns
NC
Symbol Definitions
Symbol
Definition
Clock Transition Definitions
Name
Modelica ID
Set input
set
Reset input
reset
Positive edge-triggered clock input
clock
Data input
dataIn
Data output
dataOut
Default
Units
[1]
function selection by [reset, set] reading
ResetSetMap
Output strength
strength
Data width
n
The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.
See Also
Digital Components
Digital Registers
Electrical Library
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